Volume 1 Number 1, December 2003
Computing and Information Sciences is a peer reviewed journal that is committed to timely publication of original research, surveying and tutorial contributions on the analysis and development of computing and information science. The journal is designed mainly to serve researchers and developers, dealing with information and computing. Papers that can provide both theoretical analysis, along with carefully designed computational experiments, are particularly welcome. The journal is published 2-3 times per year with distribution to librarians, universities, research centers, researchers in computing, mathematics, and information science. The journal maintains strict refereeing procedures through its editorial policies in order to publish papers of only the highest quality. The refereeing is done by anonymous Reviewers. Often, reviews take four months to six months to obtain, occasionally longer, and it takes an additional several months for the publication process.
Paper 1: Efficient Cellular Automata for Planar Graph and VLSI Layout Homotopic Compaction
Efficient Cellular Automata for Planar Graph and VLSI Layout Homotopic Compaction
Fawaz S. Al-Anzi
Abstract: One-dimensional homotopic compaction is defined as; In a given routable layout, a layout of minimum width is reachable by operations that can move each module horizontally as a unit, also deform lines maintaining their connections and maintain their routability. This paper exploits the nature of parallelism of this problem and introduces an efficient cellular automata algorithm for homotopic compaction of layouts of planar graphs and VLSI circuits. The proposed algorithm inputs a bitmap representation of a routable initial layout and produces a feasible layout of minimum width. The proposed algorithm achieves a speed up of O(N2logN) over the best known sequential algorithm. It also solves the problem of automatic jog introduction effectively. The algorithm is implemented on CAM6, a cellular automata machine developed by Tom Toffoli [19] at MIT. The proposed algorithm has good performance measures in terms of total area, total wire length, total number of bends and module distribution of a layout. The implementation objectives of minimizing the number of bits per processing element and reducing the time complexity of the overall task are also studied. The results show that the compacted bitmap representation of a planar graph, and hence a VLSI layout, is a potential approach to high performance computing in CAD environments by using a cellular automata machine as an inexpensive accelerator.
Paper 2: Performance Modeling of a Power Management/Control System
Performance Modeling of a Power Management/Control System
Reda Ammar, Howard Sholl and Ahmed Mohamed
Abstract:This paper develops a performance model for a class of soft real time systems. The incentive came from a specific commercial system; however the resulting model can have other applications. The model incorporates a set of properties that are not all common in prior models such as a queueing network with a polled serving pattern, programmable priority levels, multiple message classes, network-load-dependent multiple service, and a subset of queues with direct feedback. The analytical model can estimate performance parameters for both the overall queuing network and its specific queues. The model can be used to aid design decisions at an early stage, and can be used for later system calibration and diagnosis. Both the performance model and a sample application are described.
Paper 3: Towards Neural Network Model
for Insulin/Glucose in Diabetics Author didn't abide by
the payment rules of the journal ***
Towards
Neural Network for Insulin/Glucose in Diabetics
Raed Abu
Zitar
Abstract: In this work we look for a
general neural network model
that resembles the interactions between glucose concentration levels and amount of insulin injected in the bodies of
diabetics. We use real data for 70 different patients of diabetics and build
on it our model. Two types of neural networks (NN’s) are experimented in building that model; the first type is
called the Levenberg-Marquardt (LM) training algorithm of multilayer feed
forward neural network (NN), the other one is based on Radial Basis Function
(RBF) neural network. We do comparisons between the two models based on their
performance. The design stages mainly consist of training, testing, and
validation. A linear regression
between the output of the multi-layer feed forward neural network trained by
LM algorithm (abbreviated by LM NN) and the actual outputs shows that the LM
NN is a better model. This model can
be potentially used to build a
theoretical general regulator controller for insulin injections and, hence,
can reflect an idea about the types and amounts of insulin required for
patients.
Paper 4: Converting BPSL Behavioral Specification to FSP Using A Java-Based ParserGenerator
Converting BPSL Behavioral Specification to FSP Using a Java-Based Parser Generator
Toufik Taibi
Abstract: Balanced Pattern Specification Language (BPSL) can be used to formally specify design patterns and their combination. BPSL uses a subset of First Order Logic (FOL) to specify the structural aspect of design patterns and a subset of Temporal Logic of Actions (TLA) to specify their behavioral aspect. BPSL as any other language requires a lexical analyzer (lexer) and a parser in order to allow its users to check the lexical and syntactic correctness of their specification. Writing lexers and parsers from scratch can be a tedious and error prone process. As such, lexers and parsers generation tools have been developed to automate this task. This paper describes how both Java-based Lexer (JLex) and Constructor of Useful Parsers (CUP) were successfully used to generate highly optimized Java-based lexer and parser for BPSL. Moreover CUP was used to convert BPSL behavioral specifications to the well-known Finite State Processes (FSP) specifications in order to use Labeled Transaction System Analyzer (LTSA) model checking tool.
Paper 5: Verification of Pipelined Microprocessors Using Invariants
Verification of Pipelined Microprocessors Using Invariants
Moustafa
Bourahla
Abstract: This paper presents a new approach for the verification of a pipelined microprocessor which is based on the definition of invariants to characterize the reachable states of the pipelined machine. To express many machine-relevant properties, we have modeled the stream of instructions with the system Maude which is based on Rewriting Logic. It is also used to run and debug the pipelined machine specification. The meta-level module ITP (Inductive Theorem Prover) is used to verify the pipelined machine properties, presented as its object level specification, and eventually to verify a complete pipelined machine design, whose correctness is defined using the idea of pipeline flushing.
Paper 6: On the Availability of
Replicated Contents in the Web Author didn't abide by
the payment rules of the journal ***
On
the Availability of Replicated Contents in the Web
Fathi
Tenzakhti, Khaled Day, Mohamad Ould-Khoua
Abstract:
This study considers the
problem of locating proxies in the Web in order to maximize object
availability. A read one/write-all protocol is used and a placement based on
the Dynamic Programming (DP) technique is presented. The study then derives
the properties of the resulting replicated system and analyses its
availability as a function of the read write ratio for uniform client
requests.
Contacts
Editor-in-Chief
Prof. Jihad Mohamad Alja'am
Department of Computer Science & Computer Engineering
Qatar University - College of Engineering
P.O. Box 2713, Qatar
Email: editor@ijcis.info
The
Journal Secretary
Eng. Dana Bandok
Ontario, Canada
Email: info@ijcis.info